The memory industry is under constant pressure to reduce component size. One way that is being used to reduce component size is to fabricate memory devices as a three-dimensional (3D) memory device. This type of memory device can be achieved by forming a stack of memory cells vertically on a substrate, stacking a plurality of interconnected memory dies vertically within a single integrated circuit package, or some combination of these methods.
Multiple stacked memory dies in a memory package can be coupled (e.g., electrically connected) using vertical connectors, such as through-silicon vias (TSV) or other 3D conductive structures. Vias extend (at least partially) through a thickness of one or more of the dies and can be aligned when the dies are stacked, thus providing electrical communication among the dies in the stack. Such vias are often formed of a conductive material, such as aluminum or copper.
Once the integrated circuit dies are stacked and connected through the vias, it can be difficult to determine the location of a fault in the via stack. There are resulting needs for determining via stack faults.